1. Field of the Invention
The present invention relates to a method of manufacturing a crystalline semiconductor film formed on a substrate, and more particularly to a semiconductor device having a circuit constructed of a thin film transistor (hereinafter referred to as TFT) that uses the crystalline semiconductor film as an active layer and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and to electronic equipment having such an electro-optical device mounted thereon as a part.
It is to be noted that a semiconductor device as stated herein throughout the present specification denotes a general device which functions by utilizing semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipments are all semiconductor devices.
2. Description of the Related Art
In a method of manufacturing a semiconductor device employing a semiconductor substrate such as a silicon wafer, impurities such as heavy metallic elements are introduced into the substrate through a process contamination whereby the semiconductor device deteriorates and results in a reduction in yield. Therefore, an ultra-clean-technology has been proposed as a technique to remove these impurities from the source and its utility as an impurity remover has been proven. On the other hand, in a semiconductor process technique, a gettering technique for eliminating and capturing the impurities from an active region of the device is relatively inexpensive, and hence has procured sound achievements in the improvement of yield.
Conventional gettering techniques are roughly and conveniently divided into three methods: (1) Extrinsic Gettering: EG method, (2) Intrinsic Gettering: IG method, and (3) Chemical Gettering: CG method.
The extrinsic gettering (EG) method is a gettering technique for supplying a gettering sink to the back surface of the wafer by way of the extrinsic means. Therefore, the EG method is also called a backside gettering. The gettering sink in the EG method is imparted to the back surface of the wafer by the extrinsic means (a mechanical damage typified by a sand blasting which uses the polishing powder of SiO2 or the like, a high concentration diffusion of phosphorus, CVD growth of an Si3N4 film or a polysilicon film, etc.).
A distorted region, a stress region, a defect region, or a chemically active region formed on the back surface of the wafer operates as the gettering sink, which is due to the above-mentioned extrinsic means, to capture the impurities that have diffused to a distance which corresponds to a thickness from the front surface of the wafer. Thus, the gettering sink must be provided in the back surface of the wafer before the initial oxidation process. One of the drawbacks of the EG method is that the process employing the EG method itself may introduce new impurities into the front surface of the wafer. However, the EG method, which inflicts mechanical damages to the back surface of the wafer, is widely and generally used in the manufacturing of devices for reasons of its simplicity and low cost.
The intrinsic gettering (IG) method is a gettering technique which utilizes a bulk defect that is induced in the silicon wafer by heat treatment. That is, the IG method is also called an internal gettering because it employs a sink in the wafer.
Further, the chemical gettering (CG) method is a gettering technique which forms metal chlorides susceptible to evaporation by performing heat treatment under an atmosphere containing chloric gas to thereby remove contaminants from the front surface of the wafer. Dissimilar from the above EG method and IG method, the CG method does not supply a gettering sink. Note that the frequency of use of the CG method, compared with that of the EG method or the IG method, is not much.
Many have acknowledged that characteristics of semiconductor devices are enhanced by employing the above-mentioned gettering techniques, and hence the EG method which is suitable as a mass production technique is being actively adopted and developments for a more superior gettering techniques and simpler and easier methods have been examined as well. Although the IG effect was discovered and there was an academic rise in the interest in the gettering techniques, and even a model of a gettering phenomenon was proposed, industrial applications preceded all these. The mechanism of a gettering in which physical constants and chemical constants such as an individual saturation, a diffusion coefficient, a level of solid solution, and a segregation coefficient of the impurities formed of heavy metal elements in the silicon crystal are taken into consideration has been made clear only recently.
A technique for structuring a thin film transistor (TFT) using a semiconductor thin film (having a thickness on the order of about several to several hundred nm) formed on a substrate having an insulating surface has been attracting much attention in recent years. Thin film transistors are widely applied to electronic devices such as an IC or an electro-optical device, and in particular, development of the TFT as a switching element of an image display device is proceeding rapidly.
Conventionally, an amorphous silicon film was used in the formation of the TFT. However, attempts have been made in manufacturing the TFT by utilizing a crystalline silicon film (also referred to as a polycrystal silicon film or a polysilicon film) in order to attain a higher performance.
A technique as one of the techniques for obtaining the crystalline silicon film on a glass substrate is disclosed in Japanese Patent Application Laid-open No. Hei 8-78329. The technique disclosed in this application is one in which a metallic element for promoting crystallization to the amorphous silicon film is selectively doped, and then heat treatment is carried out to thereby form the crystalline silicon film spreading from a doped region as the starting point.
This technique is a technique in which the metallic element (such as Ni) for promoting crystallization to the amorphous silicon film is selectively doped, and then heat treatment is conducted to thereby form the crystalline silicon film spreading from the doped region as the starting point. Further, due to an action of the metallic element in this technique, a lowering of the crystallization temperature of the amorphous silicon film by approximately between 50 to 100° C. of is possible compared with the case where the metallic element to promote crystallization is not used. Thus, the time necessary for performing crystallization in this technique can also be reduced to between one fifth and one tenth compared with the case where the metallic element to promote crystallization is not used.
Despite having excellent merits in lowering the temperature and shortening the time of the crystallization process, in this technique, the metallic element (such as Ni) used in promoting crystallization forms deep levels in the silicon film to trap carriers, and hence there is concern that this will exert a bad influence on the reliability and electric characteristic of the TFT. Therefore, similar to the method of manufacturing the semiconductor device employing the above-mentioned semiconductor substrate, after crystallizing the silicon film, it is preferable that either gettering is performed to swiftly remove the metallic element or the metallic element is reduced to a level where the electric characteristic of the TFT is not influenced.
As one of the gettering methods of the metallic element (Ni), a gettering process was conceived. That is, in this gettering process, after the metallic element is doped into the amorphous silicon film formed on an insulating surface, phosphorus (P) is doped into a portion of the crystalline silicon film which was formed by performing heat treatment. Then, Ni is gettered from a region serving as the active layer of the TFT by performing heat treatment.
However, because a dosage of 2×1015 (atoms/cm3) of phosphorus is doped into the amorphous silicon film in the above gettering process, there is an extremely high possibility of bringing about a new problem in that a chemical contamination is generated inside the clean room. In addition, a phosphorus contamination in the furnace, which occurs when a substrate doped with phosphorus is placed in a furnace, also becomes a problem. In practice, a considerably high concentration of phosphorus has been detected not only in the vicinity of the doping device but also in other areas in the clean room. Phosphorus is deemed as one of the major causes of making the controlling of a threshold value of the TFT difficult.